1. Field of the Invention
The present invention relates to package stack devices and fabrication methods thereof, and more particularly, to a package stack device and a fabrication method thereof for improving the stack yield.
2. Description of Related Art
Along with the development of semiconductor packaging technologies, various types of packages haven been developed for semiconductor devices. In order to further enhance electrical performance and save packaging spaces, a plurality of package structures are stacked on one another to form a POP (package on package) device. As such, electronic elements having different functions, such as memories, CPUs(central processing units), GPUs (graphics processing units), image application processors and the like, can be integrated together so as to be applied in various kinds of compact-sized and low-profiled electronic products. FIG. 1 schematically illustrates a cross-sectional view of a conventional package stack device.
Referring to FIG. 1, a second package structure 1b is stacked on a first package structure 1a. 
The first package structure 1a has a first substrate 11 having a first surface 11a and a second surface 11b opposite to the first surface 11a, and a first electronic element 10 disposed on the first surface 11a and electrically connected to the first substrate 11. The second package structure 1b has a second substrate 12 having a third surface 12a and a fourth surface 12b opposite to the third surface 12a, and a second electronic element 15 disposed on the third surface 12a and electrically connected to the second substrate 12. Further, a plurality of solder balls 110 are formed on the first surface 11a of the first substrate 11 so as for the fourth surface 12b of the second substrate 12 to be stacked thereon and electrically connected to the first substrate 11. Furthermore, the second surface 11b of the first substrate 11 has a plurality of ball pads 112 for mounting solder balls 14. The first and second electronic elements 10, 15 can be active components and/or passive components. Referring to the drawing, the first and second electronic elements 10, 15 can be electrically connected to the substrates 11, 12, respectively, in a flip-chip manner and an underfill 13 can fill the gap therebetween so as to form flip-chip bonding structures.
However, since the second package structure 1b is stacked on the first package structure 1a by soldering, the surfaces of the first and second package structures 1a, 1b can be easily contaminated by the solder material of the solder balls 110 during the reflow process. Further, variation in the size of the solder balls 110 is not easy to control, which can easily result in a tilted stack between the two package structures and even cause positional deviation of joints between the two package structures.
Furthermore, to increase the stack height, the diameter of the solder balls 110 must be increased, thus increasing the area of the surfaces (the first surface 11a and the fourth surface 12b) occupied by the solder balls 110 and consequently reducing spaces available for layout of the electronic elements and circuits.
Moreover, increased size of the solder balls 110 can easily cause bridging between the solder balls, thus reducing the product yield.
In addition, the second package structure 1b is only supported by the solder balls 110 on the first package structure 1a such that a big gap exists between the first and second package structures 1a, 1b. Therefore, warpage can easily occur to the first and second substrates 11, 12.
Therefore, there is a need to provide a package stack device and a fabrication method thereof so as to overcome the above-described drawbacks.